In the integrated circuit (IC) industry today, billions of semiconductor devices are built on a single substrate, generally referred to as a wafer. The current demands for high density and performance associated with ultra large scale integration entail the use of submicron features, increased transistor and circuit speeds and improved reliability.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per wafer area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down introduces challenges in maintaining process variations at acceptable levels within a wafer, wafer to wafer (WtW), and lot to lot. For example, as process geometries continue to decrease, critical dimension (CD) of features of a wafer are becoming continually smaller, and variations in the CD across the wafer are increasing. The “CD” may refer to the smallest dimension of a feature along a given direction, such as a transistor gate width or a line width of other type of device feature. As CD variation increases, variation of performance characteristics of devices of the wafer also increase. For example, performance characteristics of transistors of a wafer, such as saturation drain current and threshold voltage, fluctuate with the CD variation of transistor features of a wafer, such as gate widths, spacer widths, other features of the transistors, or combinations thereof. The fluctuating performance characteristics of the transistors can lead to poor device performance and low yield.
In part because of the scaling down process described in the foregoing, inspection and measurement of surface features has become more important. Some features have especially important effects on final product function, performance, or reliability, and so their dimensions (e.g., CDs) are to be carefully controlled. Deviations of a feature's CD and cross-sectional shape, e.g., profile, from design dimensions may adversely affect the performance of the finished semiconductor device.
Therefore, there is an ongoing need to improve CDs associated with a wafer and CDs WtW.